1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device in which the same data can be written into a plurality of sets of memory cells and at the same time.
2. Description of the Related Art
In recent years, electrically erasable programmable ROMs (EEPROMs), wherein data can be electrically written and erased, are used as memory devices in computer systems. Known as one type of an EEPROM is a so-called NAND-cell type EEPROM which excels in integration density. The NAND-cell type EEPROM comprises a plurality of memory-cell units. Each unit consists of a plurality of memory cells which are connected in series to have a source and a drain in common. The memory cells of one unit are connected to one bit line.
On the other hand, two types of EEPROMs having large storage capacity are know. The first type called "AND-type" is disclosed in H. Kume, et al. of Hitachi Seisakusho, A 1.28 .mu.m.sup.2 Contactless Memory Cell Technology for a 3 V-Only 64 Mbit EEPROM, 1992 IEDM (International Electron Device Meeting) Tech. Dig., pp. 991-993. The second type called "DINOR-type" is disclosed in H. Onoda, et al. of Mitsubishi Denki, A Novel Cell Structure Suitable for a 3 Volt Operation, Sector Erase Flash Memory, 1992 IEDM Tech. Dig., pp. 599-602.
Each of the AND-type EEPROM and the DINOR-type EEPROM comprise a plurality of memory-cell units, each formed of a plurality of memory cells connected in parallel. Each memory-cell unit is provided with only one or two selecting gates, thereby increasing the integration density of the EEPROM of either type.
Each of the memory cells incorporated in the AND-type or DINOR-type EEPROM is of FET-MOS structure in which a charge-accumulating layer (i.e., a floating gate) and a control gate are arranged one above the other. An array of the memory cells, made in the form of an integrated circuit, is provided on a p-type substrate, a p-type well formed in an n-type well which is in turn formed in a p-type substrate, or a p-type well formed in an n-type substrate.
In a NAND-type EEPROM, the drains of the memory cells are connected to bit lines by selecting gates. The sources of the memory cells are connected to source lines (i.e., reference-potential lines) by other selecting gates. The control gates of the memory cells are connected together, forming a word line which extends in a row direction.
In the field of NAND-cell type EEPROMs, a set of memory cells connected one and the same word line is called "one page," and a set of pages located between a set of drain-side selecting gates and a set of source-side selecting gates is called "NAND block" or simply "block." The data stored in one NAND block is the smallest unit of data which can be erased independently of any other data.
The operation of the NAND-cell type EEPROM will be explained, based on the assumption that the memory cell array of the EEPROM is provided, in the form of an integrated circuit, in a p-type well formed in an n-type substrate.
To erase a NAND data block stored in a selected block of memory cells, the control gates of these memory cells are set at a reference potential Vss, and a high voltage Vpp (e.g., 20 V) is applied to the p-type well and the n-type substrate. The floating gate of every memory cell of the selected block emits electrons into the substrate. As a result, the threshold voltage of every memory cell decreases, and the memory cell comes to assume a specific state which will be referred to as "1" state. To erase all data stored in the memory as a whole, it suffices to select all NAND-cell blocks of the memory.
To write data into a selected NAND-cell block, a voltage is sequentially applied to the memory cells--first to the cell remotest from the bit line, and last to the cell closest to the bit line. To state more precisely, a high voltage Vpp (e.g., 20 V) is applied to the control gate of any memory cell selected in the NAND cell block, and an intermediate voltage Vm (e.g., 10 V) is applied to the control gate of any memory cell not selected in the NAND block. Either the reference potential Vss or the intermediate voltage Vm is applied to the bit line. Which voltage, Vss or Vm, should be applied to the bit line depends on the data to be written. If the reference potential Vss is applied to the bit line, it is eventually transferred to any selected memory cell. Electrons are thereby injected into the floating gate of the selected memory cell. As a result, the threshold voltage of the cell increases, and the memory cell comes to assume a specific state which will be referred to as "0" state. If the intermediate voltage Vm is applied to the bit line, no electrons are injected into each memory cell connected to the bit line. In this case, the threshold voltage of the cell does not change, remaining at a negative value.
In the data-writing mode, when a control gate line is selected, one-page data (e.g., data of 256 bytes) stored in data latch circuits can be stored altogether into the memory cells which are connected to the control gate line selected.
To the user of the NAND-cell type EEPROM, it is desirable, to facilitate the management of data stored in the EEPROM, that one-page data be copied onto a plurality of control gate lines. In other words, the technique which can be called "multiplex selection and copy" is very important to the user. This is because particular data blocks are frequently moved within the memory cell array, thus rearranging them therein.
With the conventional NAND-cell type EEPROM, however, one-page data stored in the data latch circuits can be written only into those memory cells which are connected to a control gate line in a single data-writing process. Consequently, the data-writing process must be repeated in order to the same one-page data into two or more sets of memory cells.
A memory having a great storage capacity, the NAND-cell type EEPROM is subjected to a performance test by a manufacturer before it is shipped, or by a user after it is shipped. In the test, data items representing various patterns are written into the EEPROM, read from it and erased in it, many times, to determine whether or not the EEPROM operates well. Of the test data items, the most frequently used is one representing a continuous pattern such as checkerboard pattern. Hitherto, such a test data item is written into all sets of memory cells, one set after another. Inevitably it takes much time to determine whether or not the memory cells connected to each control gate line perform their function. The greater the storage capacity of the NAND-cell type EEPROM, the longer the test time and, hence, the higher the cost of the test.
This problem is inherent not only in the NAND-cell type EEPROM, but also in other large-capacity memories such as the AND-cell type EEPROM and the DINOR-cell type EEPROM.
As described above, with a conventional semiconductor memory having a large storage capacity, particularly a large-capacity flash memory, a data-writing process must be repeated to write the same one-page data into all sets of memory cells, one set after another, for the purpose of achieving management of stored data items or accomplishing performance test. As a consequence, a considerably long time is required for the management of data or the performance test.